Analog Circuit Design: RF Circuits: Wide band, Front-Ends, by Michiel Steyaert, Arthur H.M. van Roermund, Johan Huijsing

By Michiel Steyaert, Arthur H.M. van Roermund, Johan Huijsing

Analog Circuit layout is a vital reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the academic insurance additionally makes it compatible to be used in a sophisticated layout path.

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Additional info for Analog Circuit Design: RF Circuits: Wide band, Front-Ends, DAC's, Design Methodology and Verification for RF and Mixed-Signal Systems, Low Power and Low Voltage

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The signal must be modulated in the digital domain. It must be centered around the IF frequency that was used in the super-heterodyne transmitter. The single-hop transmitter thus requires a high-speed DAC. If we would only remove the first mixing stage and the first band-pass filter in figure 8 then we could allow the DAC to have a smaller output amplitude. If we can remove one mixing stage by using a higher frequency DAC then we do not necessarily need to have a high output amplitude. Of coarse part of the linearity problems of the DAC are then solved by the amplifier.

Here again, an automatic calibration is integrated. The signal is then applied to the direct upconversion mixers, which uses the same VCO as the receiver. At the end of the transmit chain, a multi-stage class AB output amplifier provides the final amplification to the RF signal. The on-chip VCO is fully integrated, including the tank resonator circuitry. It is the heart of a completely integrated fractional-N PLL. The oscillator frequency for the various Bluetooth channels is programmed by the digital radio control section.

Let us consider a very small increment of the input code. For a converter with infinite precision this causes some capacitances to be switched from the complementary output to the output. Before switching, as in figure 5(a), the voltage on node N1 was equal to the voltage on the complementary output Vcomp divided by the gain of the switch Asw. After switching, as in figure 5(b), the voltage on node N1 will evolve to the voltage on the output Vout divided by the gain of the switch Asw. The charging of this capacitive node causes a current flow trough the right-hand switch.

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