Analog Circuit Design Techniques at 0.5 V by Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis

By Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis Tsividis, Peter Kinget

Analog layout at ultra-low offer voltages is a crucial problem for the semiconductor study neighborhood and industry.

Analog Circuit layout ideas at 0.5V covers demanding situations for the layout of MOS analog and RF circuits at a 0.5V strength provide voltage. All layout innovations awarded are actual low voltage concepts - all nodes within the circuits are in the strength offer rails. The circuit implementations of physique and gate enter absolutely differential amplifiers also are mentioned. those development blocks let us to construct continuous-time filters, track-and-hold circuits, and continuous-time sigma delta modulators.

Current books on low voltage analog layout normally disguise thoughts for provide voltages all the way down to nearly 1V. This ebook offers novel rules and effects for operation from a lot decrease provide voltages and the innovations offered are easy circuit ideas which are largely appropriate past the scope of the awarded examples.

Analog Circuit layout strategies at 0.5V is written for analog circuit designers and researchers in addition to graduate scholars learning semiconductors and built-in circuit design.

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4 Characterization results for the body-input and gate-input OTAs The general measurement setup is shown in Fig. 17. 25 V. This signal was applied to the circuit as an input. The Tektronix P6046 differential probe was used to sense the outputs of the OTA. Extensive measurements were taken using the HP3585A spectrum analyzer. To measure common-mode and powersupply rejection ratios, the setup shown in Fig. 18 was used. 3. 5 V, and is shown in comparison to simulated results in Fig. 19. Simulations of the open-loop phase response, adjusted for board parasitic capacitances, are shown compared to measurements, in Fig.

Chatterjee, Y. Tsividis, P. 5-V Analog Circuit Techniques and Their Application to OTA and Filter Design”, IEEE Journal of Solid State Circuits, Dec. 2005, vol. 40, no. 12, pp. 2373-2387. 1 Brief theoretical overview The intrinsic gate-source capacitance, Cgs , of the device in Fig. 1) VG ,VB constant where qG is the charge on the gate, and VS , VG , VB are the voltages at the source/drain, gate and body, respectively, with respect to ground. The MOSFET gate charge can be expressed in a compact form in terms of the surface potential using a charge-sheet approximation [43,70].

Measurements and simulations of the gate-input OTA in closed loop are compared to each other in Fig. 26. Harmonic distortion of the OTA is measured in closed loop and is shown in Fig. 27. The output amplitude for a 1% total harmonic distortion is differential 712 mV peak-peak. 5 V R/2 R/2 PSRR Test Setup R/3 Vdd Fig. 18: Setup for measuring CMRR and PSRR of the OTAs. The dashed resistor is required for testing the gate-input OTA only. Open Loop Response 50 Measurement Gain (dB) Gain [dB], Phase [degrees] 0 dB Gain 0 Phase (degrees) Simulation −50 25 dB Gain Margin −100 −150 45o Phase Margin −180o −200 2 10 4 10 Frequency [Hz] 6 10 Fig.

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